Ex - Analog Intern @ Texas Instruments • EE @ DTU • Undergraduate Researcher

Priyanshu Sinha  • Peerlist

• Designed and implemented a high-performance RISC-V processor in Verilog HDL using Xilinx ISE, achieving a clock frequency of 250 MHz, demonstrating efficient pipelining and instruction execution.
• Ensured reliable performance through thorough simulation and verification. Successfully implemented key processor functionalities, delivering a reliable and scalable design.

32 Bit RISC-V Processor

Developed a cutting-edge hybrid recumbent bike with a hybrid electric drive aiming to achieve a 50% increase in energy efficiency, a 30% boost in average speed, and focusing on reducing carbon footprint by 40% while reducing C footprint.

ERAWAT - Hybrid recumbent bicycle

Hospital Management System which can register patients, schedule and cancel appointments, display total bill, search for beds and allot them and display all the doctors in the required medical field using Python and MySQL.

Hospital Management System in Python

Developed a Password Manager and Encryption tool in C.

DopePass - The Password Manager in C

• Designed a pulse width modulator module in Verilog HDL, achieving a 50% duty cycle range and a maximum frequency of 1MHz. Integrated seamlessly with existing digital systems, enhancing control precision and signal stability.